What will this training include? 

It’s basically a training and learning course on how modern technology computer systems are designed, seen from a low-level design perspective. The technology is available worldwide, but now IT Labs would like to build a team of highly skilled engineers with knowledge on creation of digital systems using HDL (Hardware Description Language) on different types of silicon architectures like CPLD, FPGA and potentially on ASIC. With support of our colleagues and partners, IT Labs has crafted a fine-tuned roadmap that will unravel the secrets of specific skillsets and craftsmanship required to have a design and verification of HDL based designs. The training will contain a lot of practical examples, projects and hands on experience in working with real FPGA and CPLD chipsets that will be configured to execute diverse types of data and signal processing. 

Chip Design with HDL 

This is a methodology that is the only way to design a custom and highly complex digital systems with use of textual modelling language that describes the behaviour of digital electronics devices. The used HDL syntax in this training will be VHDL and the target architecture will be CPLD and FPGA.  

Who can apply? 

This program will be a fit for college students in the field of technology and computer science, who’re currently in the last year of their studies, as well as computer science and engineering graduates. 

Candidate Prerequisites: 


  • Successfully passed exams on Basics of Electronics course 
  • Successfully passed exams on Digital Circuits course 
  • Good understanding of Algorithms and data structures 
  • Basic understanding of Computer Systems and Architectures 
  • Basic understanding of Embedded Systems 

Nice to have: 

  • Successfully passed exams on Advanced Electronics course 
  • Basic understanding of HW configuration with VHDL 
  • Basic knowledge in creation of electronics with digital circuits 
  • Basic knowledge of CPU/MCU architectures 
  • Basic development of SW using C or any assembly 


On Wednesday, March 22nd , starting from 5 PM CET, an Open Day for Chip Design with HDL Training will be held at the Amphitheatre on FINKI, at which IT Labs’ Chief Innovation Officer, Blagoj Kjupev, will dive into detail about FPGA – from what FPGA is and how it can be used, all the way to talking about the training program, the structure of the program, and dive a bit more into all the necessary requirements in order for applicants to be able to successfully complete the training!